Technologies for fabricating semiconductor devices, such as transistors, capacitors and the like, for ultra-high density integrated circuits have been developed which extend patterning resolution beyond that of conventional lithography (which is typically limited to about 80 nm pitch). Self-aligned multiple patterning is one such class of high resolution patterning technologies. The current state of the art multiple patterning technology contemplated for commercial production is a method known as Self-Aligned Quadruple Patterning (SAQP), which is an extrapolation of the more commonly commercially used Self-Aligned Double Patterning (SADP) technique.
Problematically, the theoretical minimum regular pitch for SAQP is about 20 nanometers (nm) using conventional lithographic techniques. Moreover, variable pitch, or variable spacing between fins in a Fin Field Effect Transistor (FinFET), is very difficult to achieve with SAQP. This is particularly the case when the pitch (i.e., the distance between repetitive features in a semiconductor device structure) is less than or equal to 32 nm. More specifically, achieving variable spacing with conventional SAQP between fins within an array of five fins or more is increasingly difficult when the spacing between fins is equal to or less than 24 nm.
This lack of variability can be very problematic in the fabrication of a variety of semiconductor devices that utilize fin arrays having both n-type and p-type fins. This is because the minimum spacing distance between an n-type fin and a p-type fin (the n-to-p spacing distance) is necessarily larger than the distance between a pair of n-type fins, therefore requiring that the fin array either have some degree of variability or become unnecessarily large in size. One such class of devices requiring both n-type and p-type FinFETs are static random access memory (SRAM) cells and other similar logic cells.
Accordingly, there is a need for a method of fabricating semiconductor devices that can achieve a more variable pitch utilizing standard lithography. There is a need to be able to apply this technology to semiconductor devices having a fin pitch of 32 nm or less and to a fin spacing of 24 nm or less. There is a specific need to be able to apply this technology to the fabrication of SRAM cells. Additionally, there is a need for a method of fabricating semiconductor devices that can achieve a pitch of 20 nm or lower.
Furthermore, there is substantial need for the ability to cut a single fin in a sea of fins without damaging neighboring fins. As fin pitch scales, this is especially challenging for pitches of roughly 32 nm or less.